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added while
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@ -46,7 +46,7 @@ the 64 bit ARM Instruction Set Architecture (ISA).
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| ------- | ------- |
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| 1 | [Hello World](./section_1/hello_world/README.md) |
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| 2 | [If Statements](./section_1/if/README.md) |
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| 3 | [While Loops](./section_1/while/README.md) |
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## Section 2 - Stuff
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42
section_1/while/README.md
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42
section_1/while/README.md
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# While Loops
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## Overview
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We have already [covered](../if/README.md) the `if` statement. A `while` loop is exactly the same with the addition of at least one branch and a label. It really is that simple.
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To illustrate this, here is a flow chart of an `if` statement (on the left) compared to a `while` loop (on the right).
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The closing brace in an `if` statement is indicated by the red arrow head. This isn't a branch, the code flow simply falls through to the statement beyond the closing brace. In the `while` loop, the behavior of the closing brace changes to be that of a branch back to just before the evaluation of the boolean condition (the "Decision").
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A new label is placed before evaluating the "Decision".
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A new unconditional branch is placed after the end of the "Code Block."
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For review, here is the assembly language for an `if` statement:
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```asm
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// Assume value of a is in x0 // 1
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// Assume value of b is in x1 // 2
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cmp x0, x1 // 3
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ble 1f // 4
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// CODE BLOCK // 5
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1: // 6
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```
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Here is the code for the `while` showing one new label and one new unconditional branch:
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```asm
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// Assume value of a is in x0 // 1
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// Assume value of b is in x1 // 2
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// 3
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1: cmp x0, x1 // 4
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ble 2f // 5
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// CODE BLOCK // 6
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b 1b // 7
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// 8
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2: // 9
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```
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Temporary label `2` on `line 9` takes the place of the line after the closing brace in a `while` loop.
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BIN
section_1/while/if01s.png
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section_1/while/if01s.png
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9
section_1/while/if02.s
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// Assume value of a is in x0
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// Assume value of b is in x1
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1: cmp x0, x1
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ble 2f
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// CODE BLOCK
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b 1b
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2:
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section_1/while/while.jpeg
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section_1/while/while01s.png
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