making room in floats for lots of sub chapters - added some language about using half precision floats

.gitignore

@@ -2,6 +2,7 @@
 *.d
 
 temp
+.DS_*
 
 # Compiled Object files
 *.slo

README.md

@@ -66,8 +66,14 @@ the 64 bit ARM Instruction Set Architecture (ISA).
 |  9 | [Casting](./section_1/casting/README.md) |
 | 10 | Floating Point |
 | .... a | [.... What Are Floating Point Numbers?](./section_1/float/what.md)
-| .... b | [.... Working with Floats](./section_1/float/working.md)
-
+| .... b | [.... Registers (simplified)](./section_1/float/working.md)
+| .... c | [.... Literals](./section_1/float/)
+| .... d | [.... `fmov`](./section_1/float/)
+| .... e | [.... Conversion To / From Integers](./section_1/float/)
+| .... f | [.... Rounding](./section_1/float/)
+| .... g | [.... Four Basic Operations](./section_1/float/)
+| .... h | [.... Selected Additional Operations](./section_1/float/)
+| .... z | [.... Half Precision Floats](./section_1/float/half.md)
 
 ## Section 2 - Bit Manipulation
 

section_1/float/half.md

@@ -0,0 +1,43 @@
+# Section 1 / Half Precision Floats
+
+TL;DR - don't use these in C and C++ without being willing to wade
+through a great deal of muck. In assembly language, it is more 
+straight forward.
+
+## Half Precision Formats in C and C++
+
+Support for half precision (16 bit) floating point values does exist but
+there is no complete agreement on how different compilers support them.
+Indeed, there are not one but two competing half precision formats out
+there. These are the IEEE and GOOGLE types. Further still, many open
+source developers have created their own implementations with
+potentially clashing naming conventions.
+
+Finally, as of this writing, there is a performance penalty to using
+half precision floating point values from C and C++ for ordinary math.
+See below:
+
+```c++
+__fp16 Foo(__fp16 g, __fp16 f) {
+	return g + f;
+}
+```
+
+compiles to:
+
+```asm
+    fcvt    s1, h1
+    fcvt    s0, h0
+    fadd    s0, s0, s1
+    fcvt    h0, s0
+    ret
+```
+
+On the other hand, if you are willing to use *intrinsics* and one of
+the SIMD instruction sets offered by ARM, then knock yourself out. Be
+aware that doing so ties your code to the ARM processor in ways which
+you might regret.
+
+## Half Precision in Assembly Language
+
+more to come

section_1/float/working.md

@@ -1,34 +1,41 @@
-# Section 1 / Working with Floating Point Numbers
+# Section 1 / Registers (Simplified)
 
 ## Overview
 
-There are four highest level ideas relating to floating point operations on AARCH64.
+There are four highest level ideas relating to floating point operations
+on AARCH64.
 
-* There is another complete register rest for floating point values.
+* There is another complete register set for floating point values.
 
 * There are alternative instructions just for floating point values.
 
-* There are exotic instructions that operate on sets of floating point values (SIMD).
+* There are exotic instructions that operate on sets of floating point
+  values (SIMD).
 
-* There are instructions to go back and forth to and from the integer registers.
+* There are instructions to go back and forth to and from the integer
+  registers.
 
 ## Floating Point Registers
 
-There will be a more detailed discussion of the floating point registers when
-exotic instructions such as SIMD are discussed. For now, it is sufficient to discuss
-the less exotic aliases of the floating point registers.
+There will be a more detailed discussion of the floating point registers
+when exotic instructions such as SIMD are discussed. For now, it is
+sufficient to discuss the less exotic aliases of the floating point
+registers.
 
-We say aliases because, like the integer registers, how you reference a floating
-point register determines how it is interpreted. Yet, the different ways you can
-refer to floating point register 0 (such as `s0` or `d0`) all share the same
-physical register.
+We say aliases because, like the integer registers, how you reference a
+floating point register determines how it is interpreted.
 
-MORE TO COME.
+For example, in the following image, note the overlap of two single
+precision floats within a single double precision floating point 
+register.
 
-## Basic Floating Point Instructions
+![regs](./regs.png)
 
-## Exotic Floating Point Instructions
+It is worth noting early and often that you should not mix dealing
+with different precisions assuming that because of the overlaps in
+space, you'll get a meaningful result.
 
-This section will be a teaser for a more thorough discussion yet to be written.
+The above image does not show the corresponding layout of *half
+precision* floating point registers. `H0` sits in the least
+significant bits of `S0` and so on.
 
-## Type Conversion Instructions