XeLabs/asm_book
2
0
Fork 0
mirror of https://github.com/pkivolowitz/asm_book.git synced 2026-06-21 02:26:59 +08:00
Code Issues Projects Releases Packages Wiki Activity

section_1/kickstart: proofing pass

Browse source 
Copyedits only; no technical content added. Changes:

- subject-verb agreement: "idea of registers were introduced" -> "was"
- "operate as the speed" -> "operate at the speed"
- fixed ungrammatical "typing as apart from X, Y is Z" (now "typing:
  apart from X, Y is Z")
- comma after "x30" in list; replaced misleading claim "x31 is also
  not available" with "x31 has a special role (explained later)".
  x31 is not unavailable -- it encodes SP or XZR depending on
  instruction context, which the earlier phrasing obscured
- "hundreds of instructions each potentially has" -> "each potentially
  with" (agreement)
- "an mnemonic" -> "a mnemonic" (/n/ is a consonant sound)
- "a concrete examples" singular/plural typo
- de-duplicated back-to-back "For example" in Mixing Register Types

Rejected: leaving the "x31 is not available" line alone -- it's an
intro chapter, but "not available" reads as "doesn't exist", which
will contradict later chapters that use SP and XZR. Kept other
simplifications (informal "that big of" phrasing, stylistic comma use)
untouched.
This commit is contained in:
Perry Kivolowitz 2026-04-19 20:09:07 -05:00
parent 8db2733883
commit 4f02c5fc66
1 changed files with 10 additions and 10 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

20
section_1/kickstart.md
View file

@ -14,14 +14,14 @@ A CPU might be on one board while RAM was on another board and had to be
accessed over a shared bus. CPUs got still smaller and faster and might accessed over a shared bus. CPUs got still smaller and faster and might
be on one chip and RAM on another set of chips. be on one chip and RAM on another set of chips.
The idea of registers were introduced a very long time ago as being The idea of registers was introduced a very long time ago as being
super fast storage that is implemented directly in the CPU. Because they super fast storage that is implemented directly in the CPU. Because they
are within the CPU, distance isn't really an issue. Similarly, because are within the CPU, distance isn't really an issue. Similarly, because
they are in the CPU, they operate as the speed of the CPU itself. they are in the CPU, they operate at the speed of the CPU itself.
Registers don't have addresses because they are not in memory. Instead Registers don't have addresses because they are not in memory. Instead
they have names and naming conventions. They have only a minimal concept they have names and naming conventions. They have only a minimal concept
of typing as apart from integer, floating point (single or double of typing: apart from integer, floating point (single or double
precision) and pointer, every other notion of "type" is syntactic sugar precision) and pointer, every other notion of "type" is syntactic sugar
provided by your language and its compiler. provided by your language and its compiler.
@ -62,8 +62,8 @@ Some register types have been left out.
Registers do not have to be declared. They simply ARE. Registers do not have to be declared. They simply ARE.
There are 32 integer registers but some, like x30 are used for specific There are 32 integer registers but some, like x30, are used for specific
purposes. x31 is also not available. purposes. x31 has a special role (explained later).
When you want a 64 bit integer operation you use an x register. For all When you want a 64 bit integer operation you use an x register. For all
other integer operations, you use a w register and further specify the other integer operations, you use a w register and further specify the
@ -99,7 +99,7 @@ you will likely never hear of them again.
Remember what RISC means? *Reduced Instruction Set*? Well, that was Remember what RISC means? *Reduced Instruction Set*? Well, that was
then. This is now. AARCH64 has an enormous instruction set - hundreds of then. This is now. AARCH64 has an enormous instruction set - hundreds of
instructions each potentially has many variations. You will be instructions, each potentially with many variations. You will be
responsible for mastering every one. responsible for mastering every one.
Kidding - you won't be responsible for too too many. Relatively few. Kidding - you won't be responsible for too too many. Relatively few.
@ -118,7 +118,7 @@ CISC (Complex Instruction Set Computer) nature of the Intel processors.
The x86 and x64 ISA has variable length instructions ranging from 1 to The x86 and x64 ISA has variable length instructions ranging from 1 to
15 bytes in length! Complex indeed! 15 bytes in length! Complex indeed!
Every instruction is specified by an mnemonic consisting of some letters Every instruction is specified by a mnemonic consisting of some letters
which the *assembler* converts into numeric *op-codes*. which the *assembler* converts into numeric *op-codes*.
Most (but not all) AARCH64 instructions have three *operands*. These Most (but not all) AARCH64 instructions have three *operands*. These
@ -134,7 +134,7 @@ means:
ra = rb op rc ra = rb op rc
``` ```
For a concrete examples: For a concrete example:
```asm ```asm
sub x0, x0, x1 sub x0, x0, x1
@ -163,8 +163,8 @@ Or:
## Mixing Register Types ## Mixing Register Types
With few exceptions, different register types cannot be part of the same With few exceptions, different register types cannot be part of the same
instruction. For example adding a 64 bit register to a 32 bit register instruction. Adding a 64 bit register to a 32 bit register cannot be
cannot be done. For example: done. For example:
Given: Given: