# ETH: Computer Architecture

## Course Overview

- University: ETH Zurich
- Prerequisites: [DDCA](https://csdiy.wiki/%E4%BD%93%E7%B3%BB%E7%BB%93%E6%9E%84/DDCA/)
- Programming Language: C/C++, Verilog
- Difficulty Level: 🌟🌟🌟🌟
- Estimated Study Time: 70+ hours

This course, taught by Professor Onur Mutlu, delves into computer architecture. It appears to be an advanced course following [DDCA](https://csdiy.wiki/%E4%BD%93%E7%B3%BB%E7%BB%93%E6%9E%84/DDCA/), aimed at teaching how to design control and data paths hardware for a MIPS-like processor, how to execute machine instructions concurrently through pipelining and simple superscalar execution, and how to design fast memory and storage systems. According to student feedback, the course is at least more challenging than CS61C, and some of its content is cutting-edge. Bilibili uploaders recommend it as a supplement to Carnegie Mellon University's 18-447 course. The reading materials provided are extensive, akin to attending a semester's worth of lectures.

The official website description is as follows:
> "We will learn the fundamental concepts of the different parts of modern computing systems, as well as the latest major research topics in Industry and Academia. We will extensively cover memory systems (including DRAM and new Non-Volatile Memory technologies, memory controllers, flash memory), new paradigms like processing-in-memory, parallel computing systems (including multicore processors, coherence and consistency, GPUs), heterogeneous computing, interconnection networks, specialized systems for major data-intensive workloads (e.g., graph analytics, bioinformatics, machine learning), etc. We will focus on fundamentals as well as cutting-edge research. Significant attention will be given to real-life examples and tradeoffs, as well as critical analysis of modern computing systems."

The programming practice involves using Verilog to design and simulate RT implementations of a MIPS-like pipeline processor to enhance theoretical course understanding. The initial experiments include Verilog CPU pipeline programming. Additionally, students will develop a cycle-accurate processor simulator in C and explore processor design options using this simulator.

## Course Resources

- Course Website: [2020 Fall](https://safari.ethz.ch/architecture/fall2022/doku.php?id=start), [2022 Fall](https://safari.ethz.ch/architecture/fall2022/doku.php?id=start)
- Course Videos: Official videos available on the course website. A [2020 version is available on Bilibili](https://www.bilibili.com/video/BV1Vf4y1i7YG/?vd_source=77d47fcb2bac41ab4ad02f265b3273cf).
- Course Textbooks: No designated textbook; each lecture has an extensive bibliography for reading.
- Course Assignments: 5 Projects, mostly related to memory and cache, detailed on the [lab page of the course website](https://safari.ethz.ch/architecture/fall2022/doku.php?id=labs).

## Resource Summary
Some universities in China have introduced this course, so interested students can find additional resources through online searches.