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90 lines
3 KiB
Markdown
90 lines
3 KiB
Markdown
# Section 2 / Floating Point
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This chapter deals exclusively with the handling of floating point
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operations on the AARCH64 platform.
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## What are Floating Point Numbers?
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Let's first begin with an understanding of what floating point numbers
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are. [That can be found here](./what.md).
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The TL;DR is that floating point numbers are approximations with double
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precision being better approximations that single precision.
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Floating point numbers have a sign bit (for signed floating points), an
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exponent which controls the range of representable numbers, and a
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mantissa that controls precision.
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## Floating Point Registers
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There are 31 general registers (the X and W registers). Similarly there
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are 31 floating point registers which are reused for single, double and
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vector (SIMD - Single Instruction Multiple Data) instructions.
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A bit more detail [is provided here](./working.md).
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## Rounding and Truncation
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Truncation is part of casting `float` and `double` to `int` and `long`.
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Rounding is important too.
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[Coverage on rounding and truncation is found here](./rounding.md).
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## Loading Floating Point Numbers into Registers
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This is a little confusing because some values can be loaded from
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arguments in the `fmov` instruction. For example, 1.0 can be `fmov`ed.
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Trying to do the same for 1.1 will fail. Remember that AARCH64
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instructions are always 32 bits wide and that floating point numbers are
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at least that size.
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[This chapter](./literals.md) covers the loading of floating numbers
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into registers. A sample program is linked below.
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## Nuances of `fmov`
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As indicated above, you can `fmov` a floating point literal into a
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register. Except when you can't. Well, mostly you can't.
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Additionally, there are some rules about using `fmov` between registers.
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[This chapter](./fmov.md) covers the nuances of using
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`fmov`.
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## Half Precision Floating Point Numbers
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Often used in Computer Graphics, half precision floats fit within 16
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bits, the size of a `short`.
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The TL;DR here is: Avoid them.
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[This chapter explains why](./half.md).
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## SIMD
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There are two types of SIMD instruction sets available in the AARCH64
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ISA but the makers of processors are not obligated to implement them on
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any particular chip.
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The first kind is NEON.
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[This is described here.](./../../not_written_yet.md)
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The second kind of Scalable Vector Extension (SVE) for which we do not
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have near-term plans to cover. SVE is not implemented on any generally
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available ARM processor including Apple Silicon.
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## Demo Programs in this Chapter
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In case you want to get right to the code, here are the demos presented
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in this chapter.
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If you receive the assembly language files with a lower case extension,
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you will need to make the `.s` extension into `.S`.
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| Link | Contents | Converged |
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| ---- | -------- | --------- |
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| [Link](./float_dump.cpp) | Deconstructs floating point values | NA |
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| [Link](./asm_rounding.S) | Demonstrates some rounding in asm | Yes |
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| [Link](./rounding.cpp) | Demonstrates some rounding in C++ | NA |
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| [Link](./literals.S) | Demonstrates dealing with floating point literals | Yes |
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