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82 lines
2.4 KiB
Markdown
82 lines
2.4 KiB
Markdown
# Section 2 / Bit Fields / Review of Newly Described Instructions
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## Overview
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Our discussion of implementing ourselves what the C / C++ compiler gives us
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led us to use six new instructions. This chapter reviews those instructions.
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## `and`
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The `and` instruction is pretty much what you would expect. It implements
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the `&` operator from C and C++. That is, the bitwise and operator.
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The `and` instruction comes in a number of flavors
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### `and` Immediate
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This is the form of the instruction we used.
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```asm
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and rd, rs, imm
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```
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This performs a bitwise and of the `imm` value with the source register
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`rs` placing the result in the destination register `rd`.
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There are limits to the bit width of `imm` because it has to fit within
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the `and` instruction. If you exceed the allowable width of `imm`, the
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assembler will be glad to insult you.
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It is possible that a `mov`
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instruction will allow your immediate value. You'd follow up with an
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`and` using a register than an immediate value.
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If your immediate value is too large for a `mov` then put the value
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in RAM and `ldr` it into a register and proceed.
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We would love to tell you what the rules are for an immediate value in
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the `and` instruction, but they are not obvious and in fact are very
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complex. Our advice, try the immediate value you have in mind and if
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it works, great. Otherwise, see above.
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A slight variation on this `and` instruction uses a register where
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the preceding one uses an immediate value.
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```asm
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and rd, rs, rm
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```
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This ands `rm` to `rs` and places the result in `rd`.
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This instruction has a variation:
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```asm
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and rd, rs, rm, *shift* num_bits
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```
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`*shift*` can be one of `lsl`, `lsr`, `asr` or `ror`.
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These mean:
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| `*shift*` | Meaning | Meaning of the Meaning |
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| --------- | ------- | ---------------------- |
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| `lsl` | logical shift left | shifts left introducing zeros on the right |
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| `lsr` | logical shift right | shifts right introducing zeros on the left |
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| `asr` | arithmetic shift right | shifts right introducing duplicates of the previous most significant bit |
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| `ror` | rotate right | shifts right introducing the bits shifted out back in from the left |
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There are other two similar `and` instructions. These are the immediate and
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the register versions of `ands`. `ands` is the same as `and` with the addition
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that the CPU's condition bits are updated by the instruction permitting a
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conditional branch to follow the instruction.
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## `bfi`
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## `mvn`
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## `lsl`
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## `orr`
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## `ubfiz`
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